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C/C++ Source or Header  |  2001-04-11  |  14.6 KB  |  369 lines
  1. #ifndef _GT64_LIB_H_
  2. #define _GT64_LIB_H_
  3.  
  4. #include "../../../samples/shared/pci_regs.h"
  5. #include "../../../samples/shared/bits.h"
  6.  
  7. #ifdef __cplusplus
  8. extern "C" {
  9. #endif
  10.  
  11.  
  12. // Supported Galileo Chip Sets
  13. typedef enum
  14. {
  15.     GT64_VERSION_64111,
  16.     GT64_VERSION_64120,
  17.     GT64_VERSION_64130
  18. } GT64_VERSION;
  19.  
  20.  
  21. // GalileoT 64XXX register definitions 
  22. enum {
  23.     // CPU/Local Master Interface
  24.     GT64_CPU_TO_LOCAL_MASTER_INTERFACE_CONFIGURATION = 0x000,
  25.     GT64_MULTI_GT_REGISTER                           = 0x120,   // apply only for 64120, 64130
  26.     // Processor Address Space
  27.     GT64_RAS_1_0_LOW_DECODE_ADDRESS             = 0x008,
  28.     GT64_RAS_1_0_HIGH_DECODE_ADDRESS            = 0x010,
  29.     GT64_RAS_3_2_LOW_DECODE_ADDRESS             = 0x018,
  30.     GT64_RAS_3_2_HIGH_DECODE_ADDRESS            = 0x020,
  31.     GT64_CS_2_0_LOW_DECODE_ADDRESS              = 0x028,
  32.     GT64_CS_2_0_HIGH_DECODE_ADDRESS             = 0x030,
  33.     GT64_CS_3_BOOT_CS_LOW_DECODE_ADDRESS        = 0x038,
  34.     GT64_CS_3_BOOT_CS_HIGH_DECODE_ADDRESS       = 0x040,
  35.     GT64_PCI_IO_LOW_DECODE_ADDRESS              = 0x048,
  36.     GT64_PCI_IO_HIGH_DECODE_ADDRESS             = 0x050,
  37.     GT64_PCI_MEMORY_0_LOW_DECODE_ADDRESS        = 0x058,
  38.     GT64_PCI_MEMORY_0_HIGH_DECODE_ADDRESS       = 0x060,
  39.     GT64_INTERNAL_SPACE_DECODE                  = 0x068,
  40.     GT64_BUS_ERROR_ADDRESS_LOW_PROCESSOR        = 0x070,
  41.     GT64_READ_ONLY_0                            = 0x078,
  42.     GT64_PCI_MEMORY_1_LOW_DECODE_ADDRESS        = 0x080,
  43.     GT64_PCI_MEMORY_1_HIGH_DECODE_ADDRESS       = 0x088,
  44.     // The following applies for 64120, 64130
  45.     GT64_PCI_1_IO_LOW_DECODE_ADDRESS            = 0x090,
  46.     GT64_PCI_1_IO_HIGH_DECODE_ADDRESS           = 0x098,
  47.     GT64_PCI_1_MEMORY_0_LOW_DECODE_ADDRESS      = 0x0a0,
  48.     GT64_PCI_1_MEMORY_0_HIGH_DECODE_ADDRESS     = 0x0a8,
  49.     GT64_PCI_1_MEMORY_1_LOW_DECODE_ADDRESS      = 0x0b0,
  50.     GT64_PCI_1_MEMORY_1_HIGH_DECODE_ADDRESS     = 0x0b8,
  51.     GT64_SCS_1_0_ADDRESS_REMAP                  = 0x0d0,
  52.     GT64_SCS_3_2_ADDRESS_REMAP                  = 0x0d8,
  53.     GT64_CS_2_0_REMAP                           = 0x0e0,
  54.     GT64_CS_3_BOOT_CS_REMAP                     = 0x0e8,
  55.     GT64_PCI_0_IO_REMAP                         = 0x0f0,
  56.     GT64_PCI_0_MEMORY_0_REMAP                   = 0x0f8,
  57.     GT64_PCI_0_MEMORY_1_REMAP                   = 0x100,
  58.     GT64_PCI_1_IO_REMAP                         = 0x108,
  59.     GT64_PCI_1_MEMORY_0_REMAP                   = 0x110,
  60.     GT64_PCI_1_MEMORY_1_REMAP                   = 0x118,
  61.     // CPU Sync Barrier - applies for 64120, 64130
  62.     GT64_PCI_0_SYNC_BARRIER_VIRTUAL_REGISTER    = 0x0c0,
  63.     GT64_PCI_1_SYNC_BARRIER_VIRTUAL_REGISTER    = 0x0c8,
  64.     // DRAM and Device Address Space
  65.     GT64_RAS_0_LOW_DECODE_ADDRESS               = 0x400,
  66.     GT64_RAS_0_HIGH_DECODE_ADDRESS              = 0x404,
  67.     GT64_RAS_1_LOW_DECODE_ADDRESS               = 0x408,
  68.     GT64_RAS_1_HIGH_DECODE_ADDRESS              = 0x40c,
  69.     GT64_RAS_2_LOW_DECODE_ADDRESS               = 0x410,
  70.     GT64_RAS_2_HIGH_DECODE_ADDRESS              = 0x414,
  71.     GT64_RAS_3_LOW_DECODE_ADDRESS               = 0x418,
  72.     GT64_RAS_3_HIGH_DECODE_ADDRESS              = 0x41c,
  73.     GT64_CS_0_LOW_DECODE_ADDRESS                = 0x420,
  74.     GT64_CS_0_HIGH_DECODE_ADDRESS               = 0x424,
  75.     GT64_CS_1_LOW_DECODE_ADDRESS                = 0x428,
  76.     GT64_CS_1_HIGH_DECODE_ADDRESS               = 0x42c,
  77.     GT64_CS_2_LOW_DECODE_ADDRESS                = 0x430,
  78.     GT64_CS_2_HIGH_DECODE_ADDRESS               = 0x434,
  79.     GT64_CS_3_LOW_DECODE_ADDRESS                = 0x438,
  80.     GT64_CS_3_HIGH_DECODE_ADDRESS               = 0x43c,
  81.     GT64_BOOT_CS_LOW_DECODE_ADDRESS             = 0x440,
  82.     GT64_BOOT_CS_HIGH_DECODE_ADDRESS            = 0x444,
  83.     GT64_Address_Decode_Error                   = 0x470,
  84.     // DRAM Configuration
  85.     GT64_DRAM_CONFIGURATION                     = 0x448,
  86.     // The following applies for 64120,64130
  87.     GT64_SDRAM_OPERATION_MODE                   = 0x474,
  88.     GT64_SDRAM_BURST_MODE                       = 0x478,
  89.     GT64_SDRAM_ADDRESS_DECODE                   = 0x47c,
  90.     // DRAM Parameters
  91.     GT64_DRAM_BANK0_PARAMETERS                  = 0x44c,
  92.     GT64_DRAM_BANK1_PARAMETERS                  = 0x450,
  93.     GT64_DRAM_BANK2_PARAMETERS                  = 0x454,
  94.     GT64_DRAM_BANK3_PARAMETERS                  = 0x458,
  95.     // Device Parameters
  96.     GT64_DEVICE_BANK0_PARAMETERS                = 0x45c,
  97.     GT64_DEVICE_BANK1_PARAMETERS                = 0x460,
  98.     GT64_DEVICE_BANK2_PARAMETERS                = 0x464,
  99.     GT64_DEVICE_BANK3_PARAMETERS                = 0x468,
  100.     GT64_DEVICE_BOOT_BANK_PARAMETERS            = 0x46c,
  101.     // ECC - applies for 64130
  102.     GT64_ECC_UPPER_DATA                         = 0x480,
  103.     GT64_ECC_LOWER_DATA                         = 0x484,
  104.     GT64_ECC_FROM_MEMORY                        = 0x488,
  105.     GT64_ECC_CALCULATED                         = 0x48c,
  106.     GT64_ECC_ERROR_REPORT                       = 0x490,
  107.     // DMA Record
  108.     GT64_CHANNEL_0_DMA_BYTE_COUNT               = 0x800,
  109.     GT64_CHANNEL_1_DMA_BYTE_COUNT               = 0x804,
  110.     GT64_CHANNEL_2_DMA_BYTE_COUNT               = 0x808,
  111.     GT64_CHANNEL_3_DMA_BYTE_COUNT               = 0x80c,
  112.     GT64_CHANNEL_0_DMA_SOURCE_ADDRESS           = 0x810,
  113.     GT64_CHANNEL_1_DMA_SOURCE_ADDRESS           = 0x814,
  114.     GT64_CHANNEL_2_DMA_SOURCE_ADDRESS           = 0x818,
  115.     GT64_CHANNEL_3_DMA_SOURCE_ADDRESS           = 0x81c,
  116.     GT64_CHANNEL_0_DMA_DESTINATION_ADDRESS      = 0x820,
  117.     GT64_CHANNEL_1_DMA_DESTINATION_ADDRESS      = 0x824,
  118.     GT64_CHANNEL_2_DMA_DESTINATION_ADDRESS      = 0x828,
  119.     GT64_CHANNEL_3_DMA_DESTINATION_ADDRESS      = 0x82c,
  120.     GT64_CHANNEL_0_NEXT_RECORD_POINTER          = 0x830,
  121.     GT64_CHANNEL_1_NEXT_RECORD_POINTER          = 0x834,
  122.     GT64_CHANNEL_2_NEXT_RECORD_POINTER          = 0x838,
  123.     GT64_CHANNEL_3_NEXT_RECORD_POINTER          = 0x83c,
  124.     // The following applies for 64120, 64130
  125.     GT64_CHANNEL_0_CURRENT_DESCRIPTOR_POINTER   = 0x870,
  126.     GT64_CHANNEL_1_CURRENT_DESCRIPTOR_POINTER   = 0x874,
  127.     GT64_CHANNEL_2_CURRENT_DESCRIPTOR_POINTER   = 0x878,
  128.     GT64_CHANNEL_3_CURRENT_DESCRIPTOR_POINTER   = 0x87c,
  129.     // DMA Channel Control
  130.     GT64_CHANNEL_0_CONTROL                      = 0x840,
  131.     GT64_CHANNEL_1_CONTROL                      = 0x844,
  132.     GT64_CHANNEL_2_CONTROL                      = 0x848,
  133.     GT64_CHANNEL_3_CONTROL                      = 0x84c,
  134.     // DMA Arbiter
  135.     GT64_ARBITER_CONTROL                        = 0x860,
  136.     // Timer Counter
  137.     GT64_TIMER_COUNTER_0                        = 0x850,
  138.     GT64_TIMER_COUNTER_1                        = 0x854,
  139.     GT64_TIMER_COUNTER_2                        = 0x858,
  140.     GT64_TIMER_COUNTER_3                        = 0x85c,
  141.     GT64_TIMER_COUNTER_CONTROL                  = 0x864,
  142.     // PCI Internal
  143.     GT64_PCI_0_COMMAND                          = 0xc00,
  144.     GT64_PCI_0_TIME_OUT_RETRY                   = 0xc04,
  145.     GT64_PCI_0_RAS_1_0_BANK_SIZE                = 0xc08,
  146.     GT64_PCI_0_RAS_3_2_BANK_SIZE                = 0xc0c,
  147.     GT64_PCI_0_CS_2_0_BANK_SIZE                 = 0xc10,
  148.     GT64_PCI_0_CS_3_BOOT_CS_BANK_SIZE           = 0xc14,
  149.     GT64_PCI_0_BASE_ADDRESS_REGISTERS_ENABLE    = 0xc3c,
  150.     GT64_PCI_0_CONFIGURATION_ADDRESS            = 0xcf8,
  151.     GT64_PCI_0_CONFIGURATION_DATA               = 0xcfc,
  152.     // The following applies for 64120, 64130
  153.     GT64_PCI_1_COMMAND                          = 0xc80,
  154.     GT64_PCI_1_TIME_OUT_RETRY                   = 0xc84,
  155.     GT64_PCI_1_RAS_1_0_BANK_SIZE                = 0xc88,
  156.     GT64_PCI_1_RAS_3_2_BANK_SIZE                = 0xc8c,
  157.     GT64_PCI_1_CS_2_0_BANK_SIZE                 = 0xc90,
  158.     GT64_PCI_1_CS_3_BOOT_CS_BANK_SIZE           = 0xc94,
  159.     GT64_PCI_1_BASE_ADDRESS_REGISTERS_ENABLE    = 0xcbc,
  160.     GT64_PCI_0_PREFETCH_MAX_BURST_SIZE          = 0xc40,
  161.     GT64_PCI_1_PREFETCH_MAX_BURST_SIZE          = 0xcc0,
  162.     GT64_PCI_0_SCS_1_0_BASE_ADDRESS_REMAP       = 0xc48,
  163.     GT64_PCI_1_SCS_1_0_BASE_ADDRESS_REMAP       = 0xcc8,
  164.     GT64_PCI_0_SCS_3_2_BASE_ADDRESS_REMAP       = 0xc4c,
  165.     GT64_PCI_1_SCS_3_2_BASE_ADDRESS_REMAP       = 0xccc,
  166.     GT64_PCI_0_CS_2_0_BASE_ADDRESS_REMAP        = 0xc50,
  167.     GT64_PCI_1_CS_2_0_BASE_ADDRESS_REMAP        = 0xcd0,
  168.     GT64_PCI_0_CS_3_BOOT_CS_ADDRESS_REMAP       = 0xc54,
  169.     GT64_PCI_1_CS_3_BOOT_CS_ADDRESS_REMAP       = 0xcd4,
  170.     GT64_PCI_0_SWAPPED_SCS_1_0_BASE_ADDRESS_REMAP       = 0xc58,
  171.     GT64_PCI_1_SWAPPED_SCS_1_0_BASE_ADDRESS_REMAP       = 0xcd8,
  172.     GT64_PCI_0_SWAPPED_SCS_3_2_BASE_ADDRESS_REMAP       = 0xc5c,
  173.     GT64_PCI_1_SWAPPED_SCS_3_2_BASE_ADDRESS_REMAP       = 0xcdc,
  174.     GT64_PCI_0_SWAPPED_CS_3_BOOTCS_BASE_ADDRESS_REMAP   = 0xc64,
  175.     GT64_PCI_1_SWAPPED_CS_3_BOOTCS_BASE_ADDRESS_REMAP   = 0xce4,
  176.     GT64_PCI_1_CONFIGURATION_ADDRESS                    = 0xcf0,
  177.     GT64_PCI_1_CONFIGURATION_DATA                       = 0xcf4,
  178.     GT64_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER   = 0xc30,
  179.     // Interrupts
  180.     GT64_INTERRUPT_CAUSE                        = 0xc18,
  181.     GT64_CPU_TO_LOCAL_MASTER_MASK               = 0xc1c,
  182.     GT64_PCI_0_MASK                             = 0xc24,
  183.     GT64_PCI_0_SERR_MASK                        = 0xc28,  
  184.     GT64_INTERRUPT_ACKNOWLEDGE                  = 0xc34,  
  185.     // The following applies for 64120, 64130
  186.     GT64_HIGH_INTERRUPT_CAUSE_REGISTER          = 0xc98,
  187.     GT64_CPU_HIGH_INTERRUPT_MASK_REGISTER       = 0xc9c,
  188.     GT64_PCI_0_HIGH_INTERRUPT_CAUSE_MASK_REGISTER = 0xca4,
  189.     GT64_PCI_1_SERR1_MASK                       = 0xca8,
  190.     GT64_CPU_SELECT_CAUSE_REGISTER              = 0xc70,
  191.     GT64_PCI_0_INTERRUPT_SELECT_REGISTER        = 0xc74
  192. };
  193.  
  194. typedef struct {
  195.     DWORD AddControl:2;   // BITS 1:0
  196.     DWORD SrcDir:2;       // BITS 3:2
  197.     DWORD DstDir:2;       // BITS 5:4
  198.     DWORD DataTransLim:3; // BITS 8:6
  199.     DWORD ChainMod:1;     // BIT 9
  200.     DWORD IntMode:1;      // BIT 10
  201.     DWORD TransMod:1;     // BIT 11
  202.     DWORD ChanEn:1;       // BIT 12
  203.     DWORD FetNexRec:1;    // BIT 13
  204.     DWORD DMAActSt:1;     // BIT 14
  205.     DWORD Reserved:17;    // BITS 31:15
  206. } GT64_BITS_DMA_CHANNEL_CONTROL;
  207.  
  208.  
  209. // DMA
  210. enum { GT64_DMA_CHANNEL_SHIFT = 0x4 }; // shift in address between channels of DMA
  211.  
  212. typedef enum
  213. {
  214.     GT64_DMA_CHANNEL_0 = 0,
  215.     GT64_DMA_CHANNEL_1 = 1,
  216.     GT64_DMA_CHANNEL_2 = 2,
  217.     GT64_DMA_CHANNEL_3 = 3
  218. } GT64_DMA_CHANNEL;
  219.  
  220. typedef struct {
  221.     WD_DMA dma;
  222.     WD_DMA dmaList;
  223.     GT64_DMA_CHANNEL dmaChannel;
  224.     DWORD dwDmaControl;
  225. } GT64_DMA_STRUCT, *GT64_DMA_HANDLE;
  226.  
  227. typedef enum
  228. {
  229.     GT64_DAT_TRANS_LIM_1_BYTE = BIT8 | BIT6,
  230.     GT64_DAT_TRANS_LIM_2_BYTES = BIT8 | BIT7,
  231.     GT64_DAT_TRANS_LIM_4_BYTES = 0,
  232.     GT64_DAT_TRANS_LIM_8_BYTES = BIT6,
  233.     GT64_DAT_TRANS_LIM_16_BYTES = BIT7 | BIT6,
  234.     GT64_DAT_TRANS_LIM_32_BYTES = BIT8 | BIT7 | BIT6,
  235. } GT64_DAT_TRANS_LIM;
  236.  
  237.  
  238. // Address spaces
  239. typedef enum
  240. {
  241.     GT64_ADDR_BAR0  = AD_PCI_BAR0,
  242.     GT64_ADDR_BAR1  = AD_PCI_BAR1,
  243.     GT64_ADDR_BAR2  = AD_PCI_BAR2,
  244.     GT64_ADDR_BAR3  = AD_PCI_BAR3,
  245.     GT64_ADDR_BAR4  = AD_PCI_BAR4,
  246.     GT64_ADDR_BAR5  = AD_PCI_BAR5
  247. } GT64_ADDR;
  248.  
  249. #define GT64_ADDR_REG GT64_ADDR_BAR4
  250. #define GT64_ADDR_REG_IO GT64_ADDR_BAR5
  251.  
  252. enum { GT64_RANGE_REG = 0x00000080 };
  253.  
  254. typedef struct GT64_STRUCT *GT64_HANDLE;
  255.  
  256.  
  257. // Interrupts
  258. typedef struct
  259. {
  260.     DWORD dwCounter;   // number of interrupts received
  261.     DWORD dwLost;      // number of interrupts not yet dealt with
  262.     BOOL fStopped;     // was interrupt disabled during wait?
  263.     DWORD dwStatusReg; // value of status register when interrupt occured
  264. } GT64_INT_RESULT;
  265. typedef void (WINAPI *GT64_INT_HANDLER)( GT64_HANDLE hGT, GT64_INT_RESULT *intResult);
  266.  
  267. typedef struct
  268. {
  269.     WD_INTERRUPT Int;
  270.     HANDLE hThread;
  271.     WD_TRANSFER Trans[2];
  272.     GT64_INT_HANDLER funcIntHandler;
  273. } GT64_INTERRUPT;
  274.  
  275.  
  276. // Address Description
  277. typedef struct 
  278. {
  279.     DWORD dwMask;
  280.     DWORD dwBytes;
  281.     DWORD dwAddr;
  282.     DWORD dwAddrDirect;
  283.     BOOL  fIsMemory;
  284. } GT64_ADDR_DESC;
  285.  
  286.  
  287. // 64XXX Card structure
  288. typedef struct GT64_STRUCT
  289. {
  290.     HANDLE hWD;
  291.     WD_PCI_SLOT pciSlot;
  292.     WD_CARD_REGISTER cardReg;
  293.     GT64_ADDR_DESC addrDesc[AD_PCI_BARS];
  294.     BOOL   fUseInt;
  295.     GT64_INTERRUPT Int;
  296.     GT64_VERSION gt64Ver;
  297. } GT64_STRUCT;
  298.  
  299. enum { GT64_OPEN_USE_INT =   0x1 }; // options for GT64_Open 
  300.  
  301.  
  302.  
  303. /////////////////////
  304. // 64XXX Functions //
  305. /////////////////////
  306.  
  307. // General
  308. DWORD GT64_CountCards (DWORD dwVendorID, DWORD dwDeviceID);
  309.  
  310. BOOL GT64_Open (GT64_HANDLE *phGT, GT64_VERSION gt64Ver, DWORD dwVendorID, 
  311.                 DWORD dwDeviceID, DWORD nCardNum, DWORD dwOptions);
  312. void GT64_Close (GT64_HANDLE hGT);
  313.  
  314. BOOL GT64_IsAddrSpaceActive(GT64_HANDLE hGT, GT64_ADDR addrSpace);
  315.  
  316.  
  317. // Read / Write functions
  318. void GT64_ReadBlock (GT64_HANDLE hGT, DWORD dwOffset, PVOID buf, 
  319.                     DWORD dwBytes, GT64_ADDR addrSpace);
  320. void GT64_WriteBlock (GT64_HANDLE hGT, DWORD dwOffset, PVOID buf, 
  321.                      DWORD dwBytes, GT64_ADDR addrSpace);
  322. DWORD GT64_ReadDWord (GT64_HANDLE hGT, GT64_ADDR addrSpace, DWORD dwOffset);
  323. void GT64_WriteDWord (GT64_HANDLE hGT, GT64_ADDR addrSpace, DWORD dwOffset, DWORD data);
  324.  
  325.  
  326. // interrupt functions
  327. BOOL GT64_IntIsEnabled (GT64_HANDLE hGT);
  328. BOOL GT64_IntEnable (GT64_HANDLE hGT, GT64_INT_HANDLER funcIntHandler);
  329. void GT64_IntDisable (GT64_HANDLE hGT);
  330.  
  331.  
  332. // Register Access
  333. DWORD GT64_ReadReg (GT64_HANDLE hGT, DWORD dwReg);
  334. void GT64_WriteReg (GT64_HANDLE hGT, DWORD dwReg, DWORD dwData);
  335.  
  336.  
  337. // PCI configuration registers Access
  338. DWORD GT64_ReadPCIReg(GT64_HANDLE hGT, DWORD dwReg);
  339. void GT64_WritePCIReg(GT64_HANDLE hGT, DWORD dwReg, DWORD dwData);
  340.  
  341.  
  342. //      DMA
  343. //
  344. // Start DMA to/from card.
  345. // dwLocalAddr - local address on card to write to / read from
  346. // buf - the buffer to transfer
  347. // dwBytes - number of bytes to transfer (must be a multiple of 4)
  348. // fIsRead - TRUE: read from card to buffer.  FALSE: write from buffer to card
  349. // lim_mode - local bus width.
  350. // fmaChannel - uses channel 0-3 of the GT-64XXX
  351. GT64_DMA_HANDLE GT64_DMAOpen (GT64_HANDLE hGT, DWORD dwLocalAddr, PVOID buf, DWORD dwBytes,
  352.     BOOL fIsRead, GT64_DAT_TRANS_LIM lim_mode, GT64_DMA_CHANNEL dmaChannel);
  353. void GT64_DMAStart (GT64_HANDLE hGT, GT64_DMA_HANDLE hDma, BOOL fBlocking);
  354. void GT64_DMAClose (GT64_HANDLE hGT, GT64_DMA_HANDLE hDma);
  355. BOOL GT64_DMAIsDone (GT64_HANDLE hGT, GT64_DMA_HANDLE hDma);
  356. BOOL GT64_DMAReadWriteBlock (GT64_HANDLE hGT, GT64_ADDR addrSpace, DWORD dwLocalAddrOffset, PVOID buf, 
  357.     DWORD dwBytes, BOOL fIsRead, GT64_DAT_TRANS_LIM lim_mode, GT64_DMA_CHANNEL dmaChannel);
  358.  
  359.  
  360. // Errors
  361. extern CHAR GT64_ErrorString[]; // This string is set to an error message, if one occurs
  362.  
  363.  
  364. #ifdef __cplusplus
  365. }
  366. #endif
  367.  
  368. #endif
  369.